I am a PhD student in the EECS department at UC Berkeley, advised by Prof. Sagar Karandikar as part of the SLICE Lab. I work on computer architecture and hardware/software co-design, with a focus on hardware acceleration and the methodologies we use to build and verify chips. I am very interested in microarchitecture and hyperscale cloud datacenters and, most recently, I have started exploring ways to leverage AI for hardware design in a principled and agile way.

Before Berkeley, I spent nine months at MIT CSAIL accelerating RTL simulation through hardware–software co-design, built a Verilator-based FPGA simulation framework at Jump Trading, and fully implemented several RISC-V extensions at Semidynamics. I received a double degree in Electronic & Telecommunication Engineering and Computer Science from CFIS · UPC (Barcelona), graduating first of my class.

Beyond the lab, I am drawn to analog electronics, DSP and embedded systems. I am also a big fan of sports and nature, and I usually try to spend my free time outdoors. Some activities I absolutely love are sailing, scuba diving, BJJ, skiing, and cycling.